The present invention relates to a semiconductor device having a redistribution layer. More particularly, the redistribution layer of the semiconductor device includes a signal routing line.
Many semiconductor devices utilize wafer level packaging in integrated circuits. With wafer-level packaging, fabrication of the semiconductor device typically includes device interconnection and device protection processes, including a passivation layer over the silicon die. Bond pads typically extend out through the passivation layer for interconnection with other components of an application.
Within such processes, redistribution layers are widely used to redistribute these bond pads from one location to another. In many instances, the redistribution layer is an inexpensive way to adapt one particularly configured silicon die to several different packaging applications and assembly scenarios. Redistribution layers can therefore provide flexibility to customize a particular silicon die to various applications.
Typically, a redistribution layer is formed on top of the final passivation layer of the silicon die by relatively inexpensive processes. For example, this may be accomplished using standard photolithography and thin-film deposition techniques and electroplating. With redistribution layers, wide metal lines redistribute bond pad signals of the original silicon die, which are typically located in the center of the die, to new locations which are more convenient for the specific application, typically along the edge of the die. Typically, a redistribution layer is added to a chip after the chip is fabricated, and thus, a redistribution layer is not typically involved in the design of the internal interconnection of the chip.
For these and other reasons, there is a need for the present invention.